THE INTEGRATED CIRCUIT (IC) ERA:
Such has been the potential of the silicon integrated circuit that there has been an
extremely rapid growth in the number of transistors (as a measure of complexity) being
integrated into circuits on a single silicon chip. In less than four decades this number has rise
from only tens of transistors to potentially several hundred millions.
The relationship between the numbers of transistors per chip versus the year has been
known as 'Moore's first law' after predictions made by Gordon Moore (of Intel) in the 1960s.
Figure 1.1 also demonstrates the more accepted concept that lowering the supply voltages and
channel lengths together with increasing transistor per chip rati
efficient, smaller in size and can be packed at significantly higher density.
Although over the past several years, Silicon CMOS technology has become the dominant fabrication process for relatively high performance and the revolutionary nature of new systems such as wired and wireless communication
technologies, high-performance imaging systems, smart appliances and the like are constantly challenging the boundaries of various technology
processing requirements for the image capture, conversion, compression, decompression, enhancement and display of increasingly higher quality multimedia content and future generation multimedia, together with the emergence of new and complex optical and photonics technologies being driven by microelectronics, place heavy demands on current standard CMOS technology integrated systems, particularly when low power and high-performance solutions are required.
➡Although technology is continuously evolving to produce smaller systems with
minimized power dissipation, the IC industry is facing major challenges due to constraints on
power density (W/cm2) and high dynamic (operating) and static (standby) power di
The key to overcome these challenges lies in improvements in design, material and
manufacturing processes.
The significant issues that relate to successful designs include
(a)approach to the system design cycle
(b) workable transistors models.
