Signal Descriptions of 80386.
• CLK2: The input pin provides the basic system clock timing
for the operation of 80386.
• D0 – D31:These 32 lines act as bidirectional data bus during
different access cycles.
• A31 – A2: These are upper 30 bit of the 32- bit address bus.
• BE0 to BE3: The 32- bit data bus supported by 80386 and the
the memory system of 80386 can be viewed as a 4- byte wide
memory access mechanism. The 4 bytes enable lines BE0 to BE3, may be used for enabling these 4 blanks. Using these 4
enable signal lines, the CPU may transfer 1 byte / 2 / 3 / 4 byte
of data simultaneously.
• W/R#: The write/read output distinguishes the write and read
cycles from one another.
• D/C#: This data/control output pin distinguishes between a
data transfer cycle from a machine control cycle like interrupt acknowledge.
• M/IO#: This output pin differentiates between the memory and I/O cycles.
• LOCK#: The LOCK# output pin enables the CPU to prevent
the other bus masters from gaining the control of the system
bus.
• NA#: The next address input pin, if activated, allows address
pipelining, during 80386 bus cycles.
• ADS#: The address status output pin indicates that the address bus and bus cycle definition pins(W/R#, D/C#, M/IO#, BE0# to BE3# ) are carrying the respective valid signals. The 80383 does not have any ALE signals and so these signals may be used for latching the address to external latches.
• READY#: The ready signals indicates to the CPU that the
previous bus cycle has been terminated and the bus is ready
for the next cycle. The signal is used to insert WAIT states in a
bus cycle and is useful for interfacing of slow devices with
CPU.
• VCC: These are system power supply lines.
• VSS: These return lines for the power supply.
• BS16#: The bus size – 16 input pin allows the interfacing of 16
bit devices with the 32 bit wide 80386 data bus. Successive 16
bit bus cycles may be executed to read 32-bit data from a
peripheral.
• HOLD: The bus-hold input pin enables the other bus masters
to gain control of the system bus if it is asserted.
• HLDA: The bus-hold acknowledge output indicates that a valid bus hold request has been received and the bus has been relinquished by the CPU.
• BUSY#: The busy input signal indicates to the CPU that the
the coprocessor is busy with the allocated task.
• ERROR#: The error input pin indicates to the CPU that the
coprocessor has encountered an error while executing its instruction.
• PEREQ: The processor extension request output signal
indicates to the CPU to fetch a data word for the coprocessor.
• INTR: This interrupt pin is a maskable interrupt, that can be
masked using the IF of the flag register.
• NMI: A valid request signal at the non-maskable interrupt
request input pin internally generates a non-maskable interrupt of type2.
• RESET: A high at this input pin suspends the current operation and restart the execution from the starting location.
• N / C: No connection pins are expected to be left open while
connecting the 80386 in the circuit.
